Clock signals are essential to the coordination of various circuits. When an electronic device is produced, a series of test procedures need to be done to verify the electronic device. The test procedures, of course, should include the verification of a clock signal generator. The clock signal generator 10, which is generally an oscillator or a phase-locked loop circuit, is used to provide clock signals. Please refer to FIG. 1. A conventional device for testing the clock signals includes a frequency divider 11 and a detector 12. Since the generated clock signal Sc has a relatively high frequency, the frequency thereof is reduced by means of the frequency divider 11 and converted into a tested signal St with a divided switching frequency. The tested signal St is further sent into the detector 12 to be tested.
So far, the test procedure of the tested signal St has been only focused on the switching states of the tested signal St between two levels, i.e. a high level and a low level. That is to say, the detector 12 can only test if the tested signal St is normally switched either from the low level to the high level or from the high level to the low level, and no further check is made.
With increasing demand of high operating speed of circuits, it is important and necessary to verify accuracy of clock frequency. Therefore, it is required to perform further tests in order to verify accuracy.